The present invention relates to integrated circuits, in particular to electrostatic discharge protection of integrated circuits and to contact pads used in integrated circuits.
Electrostatic discharges (ESD) may, as is well known, damage electronic devices, particularly electronic semiconductor devices fabricated on insulating or semi-insulating substrates, such as particularly the kind of devices called integrated circuits. Devices for protecting against ESDs are conventionally incorporated in the input/output paths of most semiconductor devices in order to shunt excessive charge away from the sensitive circuits. In an integrated circuit chip, large metal areas called pads are provided which have free surfaces and area used for connecting the electronic circuits to other electrical devices, i.e., for input to and output from the electronic circuits of a chip. For example, electrically conducting wires can be bonded to such pads. Then ESD protection circuits may be located at and connected to such pads.
When making a connection to a pad, such as a wirebond connection, the downward forces can have a considerable magnitude and can cause delamination of layers below the pad, in particular if metal layers exist there. The forces can also damage pn-junctions located in that area. Thus, electronic circuits such as the ESD circuits cannot easily be located below or straightly under the pad, though such a location of some circuits would generally be advantageous since it would save a significant useful area of the chip of the integrated circuit.
In U.S. Pat. No. 5,514,892, an electrostatic discharge protection device is disclosed having diodes formed in semiconducting wells below a wirebond pad. The pad is through one diode connected to ground and through five diodes connected in series to a supply voltage of 3 V. By the provision of the latter diodes connected in series the integrated circuit is tolerant to 5 V. The diodes are formed below the pad in a pattern having six rectangular areas located in row. This construction, probably especially the particular layout of an intermediate connecting metal layer, is claimed to eliminate the problem of interlayer delamination.
In U.S. Pat. No. 4,750,081, an electrostatic discharge protection circuit is disclosed having diodes located directly beneath the rectangular corners of a wirebond pad. Also, discrete diodes may be formed directly beneath the perimeter or the marginal portion of the pad in a row between the corner diodes, the longitudinal extension of these other diodes being perpendicular to the sides of the pad. The major portion of the pad will thus have no metal layers therebelow, reducing the risk of delamination. Only diodes of a single orientation type are used connecting the metal pad to the substrate by a reverse-biased pn-junction. A protective structure is disclosed in U.S. Pat. No. 5,304,839, the structure not including any resistor in the input or output path.
In input paths of semiconductor devices, often some protection to high input currents is provided, such as an electrical resistance connected in the input path, this resistance limiting the input current. This resistance is conventionally located outside the bonding pad and then occupies some valuable chip area, as is illustrated by the documents cited below.
In U.S. Pat. No. 4,806,999 input pads are protected from electrostatic discharge by two diodes located under the periphery of the pad. The protective diodes are formed by first electrodes connected to the pad and having shapes of relatively narrow strips extending along substantially half the periphery or edge line of the pad. The first electrodes are located connected to or in tubs or wells, which have doping types opposite those of the first electrodes and which form the second electrodes of the diodes and which are intended to be connected to a supply drive voltage or ground. The boundary between the tubs are located in a region not overlaid by the exposed portion of the pad. An input resistor can be included between the pad and the input circuitry.
In U.S. Pat. No. 4,876,584 an integrated circuit is disclosed having terminal pads protected by diodes and transistors. The diodes and transistors are placed horizontally outside the respective pads and have one terminal located at the edge of the pads. A resistor is provided by a resistive path connecting a pad to the remainder of the integrated is circuit. A similar structure having protective diodes and a resistor is disclosed in the published European patent application 0 371 663, the resistor being formed by a metal silicide link placed horizontally outside the pad. Other similar protective structures including a resistor in an input and/or output path are disclosed in U.S. Pat. Nos. 5,808,343, 5,615,073, 5,196,913, 4,730,208 and 4,710,791.
It is an object of the invention to provide a device for protecting a connection pad of an integrated circuit against excessive positive or negative voltages, the device presupposing no extra processing steps when fabricating the integrated circuit.
It is an object of the invention to provide a device for protecting a connection pad of an integrated circuit against excessive positive or negative voltages having a small parasitic capacitance and having a good tolerance of electric overstress.
It is another object of the invention to provide a connection pad of an integrated circuit which has ESD protection and has a minimum risk of causing latch-up of input/output transistors.
It is another object of the invention to provide a connection pad of an integrated circuit which is protected against ESDs and has a minimum risk of delamination and of damaging pn-junctions of ESD-circuits when exposed to forces incurred when actually making a bonding to the pad, such as wire-bonding.
It is another object of the invention to provide a connection pad of an integrated circuit which has a resistance connected in an input and/or output path and provided in a simple and space-saving way.
Thus, connecting pads such as wirebond pads or pads for xe2x80x9cflip-chipxe2x80x9d contacting for integrated circuits have protective diodes formed by first electrodes which are connected to the respective pad and which have shapes of relatively narrow strips extending at or along a portion of the periphery or edge line of the pad. The first electrodes have a first doping type and are located connected to or in regions, which have a second doping type opposite the first doping type and form the second electrodes of the diodes and which are intended to be connected to sources of constant potentials capable of absorbing high currents. The location of the first electrodes at the edges of the pads allows that all metal areas required for electrically connecting the first electrodes to the pad can also be located at the edges of the pads. Hence no metal layer beneath the central large portions of the pads Is required. The regions directly below the center portions of the pads can then be made relatively uniform containing e.g. most silicon oxide what reduces the risk of delamination. Also, no pn-junctions have to located beneath said center portions.
The narrow shape of the first electrodes results in a low capacitance of the first electrodes to the second, regions and to other electrically conducting regions of the circuit. The narrow shape also provides a predetermined electrical resistance per unit length resulting in a distribution of possible high currents over the length of the first electrodes. The narrow strips of the first electrodes can be located straightly below a marginal portion of the respective pad and they can also have some portions outside that region, which thus is then will be located below surface portions at the side of the pad. The narrow strips can in many cases be given a sufficient length by making the pads octagonal having angles of substantially 135xc2x0. The strip-shaped regions are continuous strips which advantageously should have as smooth a configuration as possible and they should thus have angles not smaller than substantially 135xc2x0 in order to avoid too high electric field strengths.
Specifically, one of the strip-shaped regions is used for forming an electrical resistor in an input and/or output current path of the integrated semiconductor circuit, such a location of the resistor not requiring any extra space on the integrated circuit chip. The resistor is formed by a portion of a first doped region, all of this portion or even all of the first doped region being located straightly under the pad, particularly all of the portion and/or all of the first doped region being located under a marginal portion of the pad. The portion and/or the first doped region have preferably an elongated shape or a strip-shape with a longitudinal direction and are arranged so that electrical current passing the resistor has directions substantially perpendicular to the longitudinal direction. Then, in particular the length of and the width of the portion and/or of the first doped region can be selected to give the resistor a predetermined electrical resistance per unit length of the portion so that electrical current is distributed substantially uniformly over all of the length of the portion. The portion and/or the first doped region can advantageously have shape of a continuous strip extending in parallel to a portion of the edge of the pad. In the case where the portion and/or the first doped region have the shapes of strips, the strips preferably have corners or angles between connected portions of the strip which are at least substantially 135xc2x0.
In the preferred embodiment, the first doped region is also an electrode of a first diode protecting the integrated semiconductor circuit, the first diode being connected to the input and/or output path. The first doped region which then forms the first electrode of the first diode can then be doped to a first conductivity type and electrically connected to the pad, and a second electrode of the first diode is formed by a second doped region of a second conductivity type opposite the first conductivity type, the second doped region being a relatively large region horizontally surrounding but not underlying the first doped region. The first and second doped regions are a similar kind of regions, extending from a horizontal plane down to substantially the same depth and being the type of regions called xe2x80x9cwellsxe2x80x9d or xe2x80x9ctubsxe2x80x9d having a relatively low doping and a low conductivity. Third and fourth doped regions can be located inside, at the surface of and doped to the same type as the first region but they have higher doping and thus a higher conductivity than the first region, the third and fourth doped regions working as contact areas of the resistor formed in the material of the first doped region between these contact areas.
The first, third and fourth regions are preferably all strip-shaped and extend in parallel to each other and thus have parallel longitudinal directions. The third doped region can then be a contact area of the first electrode of the first diode, the first electrode being the first doped region. In a practical embodiment the fourth doped region is located closer to the center of the pad than the third doped region, the fourth doped region thus being protected since the first diode which acts as a protective diode is formed mainly at the outer boundary between the first and second regions, the outer boundary being more distant of the center of the pad than the opposite inner boundary. This is due to the fact that the second region is preferably connected to a constant potential at a region at some distance of the pad. All doped regions preferably have boundaries which have corners or angles between connected portions of the respective boundary which are at least substantially 135xc2x0 in order to reduce the risk of high localized electrical fields being created.
Generally also, a device for protecting an electrical connection pad of an integrated semiconductor circuit or chip against high and low voltages comprises a first well of a first conductivity type and a second well of a second conductivity type, the second conductivity type being opposite the first conductivity type, the first and second wells being formed at the surface of or in a substrate. A first conductive area of the second conductivity type is located in the first well for forming a first pn-junction and a second conductive area of the first conductivity type is located in the second well for forming a second pn-junction. The first and second conductive areas are electrically connected to the pad. A third well of the second conductivity type is located inside and is horizontally surrounded by the first well, which thus only encloses the third well at the vertical sides thereof and has no portion under the third well. The first conductive area is located inside the third well and acts as a contact area of the first pn-junction which is formed at the boundary between the first and third well.
Practically, the first conductivity type can be P-type and the second conductivity N-type, and then the doping producing the conductivity of the third well can substantially comprise phosphorous atoms and the doping producing the conductivity of the first conductive area can substantially comprise arsenic atoms.
The first and second wells can advantageously be located at the side of each other and each have portions located below substantially a half of the pad, the border line between the wells thus extending along a diameter of the pad or passing through a center of the pad.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the methods, processes, instrumentalities and combinations particularly pointed out in the appended claims.